FIG. 8 shows the configuration of a conventional semiconductor memory device. In FIG. 8, a memory cell array 1 forms a memory array divided into a plural number of segments as relief units (redundancy units). In FIG. 8, the ROW and the COLUMN of the memory cell array are divided into four segments and into two segments, respectively. A ROW address, generated by a peripheral circuit 2, is supplied to a switch (multiplexer) 3, an output of which is supplied to a ROW pre-decoder 4 and to a redundancy X-decoder (XDEC) 5. When a command for write or read access to or from a memory cell is entered, a ROW address, as an access address, supplied from outside, is selected by the switch 3 and thence transmitted to a ROW pre-decoder 4 and to the redundancy XDEC 5.
When a CBR (auto) refresh command is entered, an internal ROW address (refresh address), counted up in a CBR (Cas Before Ras) counter 6, is selected by the switch 3, based on the CBR signal, generated in accordance with the refresh signal, and thence transmitted to the ROW pre-decoder 4 and to the redundancy XDEC 5.
Outputs X3 to X12 of the ROW pre-decoder 4 are supplied to an X-decoder 7 (XDEC) to select a main word line, whilst outputs X0 to X2 are supplied to the memory cell array 1 for use for selecting a sub-word line provided with a ratio of 8 per main word line.
The count value of the CBR counter 6 is counted up each time a CBR (auto) refresh command is entered.
When an output signal (internal ROW address) of the switch 3, supplied to the redundancy XDEC 5, coincides with a ROW redundancy address, programmed in the redundancy XDEC 5, a redundancy main word line, decoded by the redundancy XDEC 5, is selected in place of a main word line decoded by the X-decoder 7. Similarly, when a COLUMN address, supplied to a redundancy YDEC 18, coincides with a redundancy COLUMN address, programmed in the redundancy YDEC 18, the selected COLUMN line, decoded by a YDEC 9, is controlled to be not selected, whilst a selected redundancy COLUMN line, decoded by the redundancy YDEC 18, is selected. In FIG. 8, the input/output circuit 12 is used for writing and reading data to and from the cell array 1.
In a conventional process for relieving fail cells in a conventional semiconductor memory device, a memory cell array forms an array divided into a plural number of segments as relief units. When an output signal of the switch 3, supplied to the redundancy XDEC 5 (internal ROW address signal) of FIG. 8, coincides with a ROW redundancy address, as programmed in the redundancy XDEC 5, the main word line, decoded by the XDEC 7, is non-selected, while a redundancy main word line, decoded by the redundancy XDEC 5, is selected.
If, in the conventional relieving process for fail cells in the conventional semiconductor memory device, a redundancy circuit is already used up in a given segment, the semiconductor memory device cannot be relieved, because the redundancy circuit has already been used up, even though there are left usable redundancy circuits in the other segments. Thus, there arises the necessity for providing more redundancy cells, thus increasing the cost of a chip.
For example, there is disclosed in Patent Document 1 a semiconductor memory device which performs refreshing for specified cells having poor refresh characteristics more frequently than other cells to relieve the specified cell to reduce the chip area as well as to reduce the costs.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-4-10297 (from page 3 right upper column line 4 to page 4 right upper column line 12 and FIGS. 1 to 3)